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M25PX32
32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface
Preliminary Data
Features

SPI bus compatible serial interface 75 MHz (maximum) clock frequency 2.7 V to 3.6 V single supply voltage Dual input/output instructions resulting in an equivalent clock frequency of 150 MHz: - Dual Output Fast Read instruction - Dual Input Fast Program instruction 32 Mbit Flash memory - Uniform 4-Kbyte subsectors - Uniform 64-Kbyte sectors Additional 64-byte user-lockable, one-time programmable (OTP) area Erase capability - Subsector (4-Kbyte) granularity - Sector (64-Kbyte) granularity - Bulk Erase (32 Mbit) in 17 s (typical with VPP = 9 V) Write protections - Software write protection applicable to every 64-Kbyte sector (volatile lock bit) - Hardware write protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2) Deep Power-down mode: 5 A (typical) Electronic signature - JEDEC standard two-byte signature (7116h) - Unique ID code (UID) +16 byte of CFI data More than 100 000 write cycles per sector More than 20 year data retention Packages - ECOPACK(R) (RoHS compliant) SO16 (MF) 300 mils SO8W (MW) 208 mils VFQFPN8 (MP) 6 x 5 mm

August 2007
Rev 2
1/63
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
M25PX32
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . 10 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dual Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . 13 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 Fast Bulk Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 14 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8.1 4.8.2 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16
4.9
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 6.2 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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M25PX32
Contents
6.3 6.4
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read Data Bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . 33 Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7 8 9 10 11 12 13
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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List of tables
M25PX32
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity) . . . . . . . . . . . . . . . 16 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SO8W 8 lead plastic small outline, 208 mils body width, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 60 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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M25PX32
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 27 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 29 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 32 Read Data Bytes at higher speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Dual Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Lock Register (RDLR) instruction sequence and data-out sequence . . . . . . . . . . . . 35 Read OTP (ROTP) instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Dual Input Fast Program (DIFP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Program OTP (POTP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 How to permanently lock the 64 OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Subsector Erase (SSE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 48 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 56 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 x 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SO8W 8 lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . . . 59 SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . . 60
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Description
M25PX32
1
Description
The M25PX32 is a 32 Mbit (4 Mb x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX32 supports two new, high-performance dual input/output instructions:

Dual Output Fast Read (DOFR) instruction used to read data at up to 75 MHz by using both pin DQ1 and pin DQ0 as outputs Dual Input Fast Program (DIFP) instruction used to program data at up to 75 MHz by using both pin DQ1 and pin DQ0 as inputs
These new instructions double the transfer bandwidth for read and program operations. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 64 sectors that are further divided into 16 subsectors each (1024 subsectors in total). The memory can be erased a 4-Kbyte subsector at a time, a 64-Kbyte sector at a time, or as a whole. It can be Write Protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64 Kbytes (sector granularity). An enhanced Fast Bulk Erase mode is available to speed up Bulk Erase operations in factory environment. The device enters this mode whenever the VPPH voltage is applied to the Write Protect/Enhanced Program supply voltage pin (W/VPP). The M25PX32 has 64 One-Time-Programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP (POTP), respectively. These 64 bytes can be permanently locked by a particular Program OTP (POTP) sequence. Once they have been locked, they become read-only and this state cannot be reverted. In order to meet environmental requirements, ST offers the M25PX32 in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK(R) is an ST trademark. ECOPACK(R) specifications are available at: www.st.com.
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M25PX32 Figure 1. Logic diagram
VCC
Description
DQ0 C S W/VPP HOLD M25PX32
DQ1
VSS
AI14228
Table 1.
Signal names
Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect/Enhanced Program supply voltage Hold Supply voltage Ground Input I/O(1) I/O(2) Input Input Input Direction
Signal name C DQ0 DQ1 S W/VPP HOLD VCC VSS
1. Serves as an output during Dual Output Fast Read (DOFR) instructions. 2. Serves as an input during Dual Input Fast Program (DIFP) instructions.
Figure 2.
VFQFPN and SO8 connections
M25PX32 S DQ1 W/VPP VSS 1 2 3 4 8 7 6 5 VCC HOLD C DQ0
AI13720b
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
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Description Figure 3. SO16 connections
M25PX32 HOLD VCC DU DU DU DU S DQ1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C DQ0 DU DU DU DU VSS W/VPP
AI13721b
M25PX32
1. DU = Don't use. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
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M25PX32
Signal descriptions
2
2.1
Signal descriptions
Serial Data output (DQ1)
This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the Dual Input Fast Program (DIFP) instruction, pin DQ1 is used as an input. It is latched on the rising edge of the Serial Clock (C).
2.2
Serial Data input (DQ0)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). During the Dual Output Fast Read (DOFR) instruction, pin DQ0 is used as an output. Data are shifted out on the falling edge of the Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (DQ0) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (DQ1) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (DQ1) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data input (DQ0) and Serial Clock (C) are Don't care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
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Signal descriptions
M25PX32
2.6
Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register. See Table 9). If VPP is in the range of VPPH (as defined in Table 14) it acts as an additional power supply during the Bulk Erase cycle. In this case VPP must be stable until the Bulk Erase algorithm is completed.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
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M25PX32
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Standby mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Bus Master and memory devices on the SPI bus
VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK C SPI Bus Master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD DQ1DQ0 SPI memory device VCC VSS R C DQ1 DQ0 SPI memory device VCC VSS R C DQ1DQ0 SPI memory device VCC VSS
Figure 4.
AI13725b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure that the M25PX32 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 k, assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance.
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SPI modes
M25PX32 Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 5. SPI modes supported
CPOL CPHA 0 0 C
1
1
C
DQ0
MSB
DQ1
MSB
AI13730
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M25PX32
Operating features
4
4.1
Operating features
Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP) and Table 17: AC characteristics).
4.2
Dual Input Fast Program
The Dual Input Fast Program (DIFP) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from 1 to 0). For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see Section 6.12: Dual Input Fast Program (DIFP)).
4.3
Subsector Erase, Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a subsector at a time, using the Subsector Erase (SSE) instruction, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSSE, tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program OTP (POTP), Program (PP), Dual Input Fast Program (DIFP) or Erase (SSE, SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
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Operating features
M25PX32
4.5
Fast Bulk Erase mode
The Fast Bulk Erase mode is used to speed up Bulk Erase operations. The device enters the Fast Bulk Erase mode during a Bulk Erase instruction whenever a voltage equal to VPPH is applied to the W/VPP pin. The use of the Fast Bulk Erase mode requires specific operating conditions in addition to the normal ones (VCC must be within the normal operating range):

the voltage applied to the W/VPP pin must be equal to VPPH (see Table 13) ambient temperature, TA must be 25 C 10 C, the cumulated time during which W/VPP is at VPPH should be less than 80 hours.
4.6
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down (RDP) instruction) is executed. While in the Deep Power-down mode, the device ignores all Write, Program and Erase instructions (see Deep Power-down (DP)), this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
4.7
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.
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M25PX32
Operating features
4.8
Protection modes
There are protocol-related and specific hardware and software protection modes. They are described below.
4.8.1
Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX32 features the following data protection mechanisms:

Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - - - - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write to Lock Register (WRLR) instruction completion Program OTP (POTP) instruction completion Page Program (PP) instruction completion Dual Input Fast Program (DIFP) instruction completion Subsector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection, as all Write, Program and Erase instructions are ignored.
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Operating features
M25PX32
4.8.2
Specific hardware and software protection
There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. SPM1 and SPM2
The first software protected mode (SPM1) is managed by specific Lock Registers assigned to each 64 Kbyte sector. The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock bit and the Lock Down bit. - Write Lock bit: The Write Lock bit determines whether the contents of the sector can be modified (using the Write, Program or Erase instructions). When the Write Lock bit is set to `1', the sector is write protected - any operations that attempt to change the data in the sector will fail. When the Write Lock bit is reset to `0', the sector is not write protected by the Lock Register, and may be modified. - Lock Down bit: The Lock Down bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down bit is set, `1', further modification to the Write Lock and Lock Down bits cannot be performed. A powerup, is required before changes to these bits can be made. When the Lock Down bit is reset, `0', the Write Lock and Lock Down bits can be changed. The definition of the Lock Register bits is given in Table 9: Lock Register out.
Table 2.
Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity)
Sector Lock Register Protection status Lock Down bit 0 0 1 1
Write Lock bit 0 1 0 1 Sector unprotected from Program/Erase/Write operations, protection status reversible Sector protected from Program/Erase/Write operations, protection status reversible Sector unprotected from Program/Erase/Write operations, Sector protection status cannot be changed except by a Power-up. Sector protected from Program/Erase/Write operations, Sector protection status cannot be changed except by a Power-up.
the second software protected mode (SPM2) uses the Block Protect bits (see Section 6.4.3: BP2, BP1, BP0 bits) and the Top/Bottom bit (see Section 6.4.4: TB bit) to allow part of the memory to be configured as read-only.
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M25PX32 Table 3. Protected area sizes
Memory content
Operating features
Status Register contents TB BP BP BP bit bit 2 bit 1 bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 none Upper 64th (Sector 63) Protected area
Unprotected area All sectors(1) (64 sectors: 0 to 63) Lower 63/64ths (63 sectors: 0 to 62)
Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61) Upper sixteenth (four sectors: 60 to 63) Upper eighth (eight sectors: 56 to 63) Lower 15/16ths (60 sectors: 0 to 59) Lower seven-eighths (56 sectors: 0 to 55)
Upper quarter (sixteen sectors: 48 to Lower three-quarters (48 sectors: 0 63) to 47) Upper half (thirty-two sectors: 32 to 63) All sectors (64 sectors: 0 to 63) none Lower 64th (sector 0) Lower 32nd (two sectors: 0 and 1) Lower 16th (four sectors: 0 to 3) Lower 8th (eight sectors: 0 to 7) Lower 4th (sixteen sectors: 0 to 15) Lower half (thirty-two sectors: 0 to 31) All sectors (64 sectors: 0 to 63) Lower half (32 sectors: 0 to 31) none All sectors(1) (64 sectors: 0 to 63) Upper 63/64ths (63 sectors: 1 to 63) Upper 31/32ths (62 sectors: 2 to 63) Upper 15/16ths (60 sectors: 4 to 63) Upper 7/8ths (56 sectors: 8 to 63) Upper 3/4ths (48 sectors: 16 to 63) Upper half (32 sectors: 32 to 63) none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more details, see Section 6.5: Write Status Register (WRSR).
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Operating features
M25PX32
4.9
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 6). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 6). During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data input (DQ0) and Serial Clock (C) are Don't care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Figure 6. Hold condition activation
C
HOLD
Hold Condition (standard use)
Hold Condition (non-standard use)
AI02029D
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M25PX32
Memory organization
5
Memory organization
The memory is organized as:

4 194 304 bytes (8 bits each) 1024 subsectors (4 Kbytes each) 64 sectors (64 Kbytes each) 16384 pages (256 bytes each) 64 OTP bytes located outside the main memory array
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Subsector, Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7.
HOLD VPP S C DQ0 DQ1 Control Logic
Block diagram
High Voltage Generator 64 OTP bytes
I/O Shift Register
Address Register and Counter
256 Byte Data Buffer
Status Register
3FFFFFh
Y Decoder
Configurable OTP area in main memory array
00000h 256 Bytes (Page Size) X Decoder
000FFh
AI13722
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Memory organization Table 4.
Sector
M25PX32 Memory organization
Subsector 1023 Address range 3FF000h ... 3FFFFFh 52 ... Sector Subsector 847 ... Address range 34F000h ... 34FFFFh ... 340FFFh 33FFFFh ... 330FFFh 32FFFFh ... 320FFFh 31FFFFh ... 310FFFh 30FFFFh ... 300FFFh 2FFFFFh ... 2F0FFFh 2EFFFFh ... 2E0FFFh 2DFFFFh ... 2D0FFFh 2CFFFFh ... 2C0FFFh 2BFFFFh ... 2B0FFFh 2AFFFFh ... 2A0FFFh
63
1008 1007 62 ...
...
3F0000h 3EF000h ...
3F0FFFh 3EFFFFh 51 ...
832 831 ...
340000h 33F000h ... 330000h 32F000h ... 320000h 31F000h ... 310000h 30F000h ... 300000h 2FF000h ... 2F0000h 2EF000h ... 2E0000h 2DF000h ... 2D0000h 2CF000h ... 2C0000h 2BF000h ... 2B0000h 2AF000h ... 2A0000h
992 991 61 ...
3E0000h 3DF000h ...
3E0FFFh 3DFFFFh 50 ...
816 815 ... 800 799 49 ... 784 783 48 ... 768 767 47 ... 752 751 46 ... 736 735 45 ... 720 719 44 ... 704 703 43 ... 688 687 42 ... 672
976 975 60 ...
3D0000h 3CF000h ...
3D0FFFh 3CFFFFh ... 3C0FFFh 3BFFFFh ... 3B0FFFh 3AFFFFh ... 3A0FFFh 39FFFFh ... 390FFFh 38FFFFh ... 380FFFh 37FFFFh ... 370FFFh 36FFFFh ... 360FFFh 35FFFFh ... 350FFFh
960 959 59 ...
3C0000h 3BF000h ... 3B0000h 3AF000g ... 3A0000h 39F000h ... 390000h 38F000h ... 380000h 37F000h ... 370000h 36F000h ... 360000h 35F000h ... 350000h
944 943 58 ... 928 927 57 ... 912 911 56 ... 896 895 55 ... 880 879 54 ... 864 863 53 ... 848
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M25PX32 Table 4.
Sector
Memory organization Memory organization (continued)
Subsector 671 41 ... Address range 29F000h ... 29FFFFh 30 ... Sector Subsector 495 ... Address range 1EF000h ... 1EFFFFh ... 1E0FFFh 1DFFFFh ... 1D0FFFh 1CFFFFh ... 1C0FFFh 1BFFFFh ... 1B0FFFh 1AFFFFh ... 1A0FFFh 19FFFFh ... 190FFFh 18FFFFh ... 180FFFh 17FFFFh ... 170FFFh 16FFFFh ... 160FFFh 15FFFFh ... 150FFFh 14FFFFh ... 140FFFh 21/63
656 655 40 ...
290000h 28F000h ...
290FFFh 28FFFFh 29 ...
480 479 ...
1E0000h 1DF000h ... 1D0000h 1CF000h ... 1C0000h 1BF000h ... 1B0000h 1AF000h ... 1A0000h 19F000h ... 190000h 18F000h ... 180000h 17F000h ... 170000h 16F000h ... 160000h 15F000h ... 150000h 14F000h ... 140000h
640 639 39 ...
280000h 27F000h ...
280FFFh 27FFFFh 28 ...
464 463 ... 448 447 27 ... 432 431 26 ... 416 415 25 ... 400 399 24 ... 384 383 23 ... 368 367 22 ... 352 351 21 ... 336 335 20 ... 320
624 623 38 ...
270000h 26F000h ...
270FFFh 26FFFFh ... 260FFFh 25FFFFh ... 250FFFh 24FFFFh ... 240FFFh 23FFFFh ... 230FFFh 22FFFFh ... 220FFFh 21FFFFh ... 210FFFh 20FFFFh ... 200FFFh 1FFFFFh ... 1F0FFFh
608 607 37 ...
260000h 25F000h ... 250000h 24F000h ... 240000h 23F000h ... 230000h 22F000h ... 220000h 21F000h ... 210000h 20F000h ... 200000h 1FF000h ... 1F0000h
592 591 36 ... 576 575 35 ... 560 559 34 ... 544 543 33 ... 528 527 32 ... 512 511 31 ... 496
Memory organization Table 4.
Sector
M25PX32 Memory organization (continued)
Subsector 319 Address range 13F000h ... 13FFFFh 8 ... Sector Subsector 143 ... Address range 8F000h ... 8FFFFh ... 80FFFh 7FFFFh ... 70FFFh 6FFFFh ... 60FFFh 5FFFFh ... 50FFFh 4FFFFh ... 40FFFh 3FFFFh ... 30FFFh 2FFFFh ... 20FFFh 1FFFFh ... 10FFFh 0FFFFh ... 04FFFh 03FFFh 02FFFh 01FFFh 00FFFh
19
304 303 18 ...
...
130000h 12F000h ...
130FFFh 12FFFFh 7 ...
128 127 ...
80000h 7F000h ... 70000h 6F000h ... 60000h 5F000h ... 50000h 4F000h ... 40000h 3F000h ... 30000h 2F000h ... 20000h 1F000h ... 10000h 0F000h ... 04000h 03000h 02000h 01000h 00000h
288 287 17 ...
120000h 11F000h ...
120FFFh 11FFFFh 6 ...
112 111 ... 96 95 5 ... 80 79 4 ... 64 63 3 ... 48 47 2 ... 32 31 1 ... 16 15 ... 4 0 3 2 1 0
272 271 16 ...
110000h 10F000h ...
110FFFh 10FFFFh ... 100FFFh FFFFFh ... F0FFFh EFFFFh ... E0FFFh DFFFFh ... D0FFFh CFFFFh ... C0FFFh BFFFFh ... B0FFFh AFFFFh A0FFFh 9FFFFh ... 90FFFh
256 255 15 ...
100000h FF000h ... F0000h EF000h ... E0000h DF000h ... D0000h CF000h ... C0000h BF000h ... B0000h AF000h A0000h 9F000h ... 90000h
240 239 14 ... 224 223 13 ... 208 207 12 ... 192 191 11 ... 176 175 10 160 159 9 ... 144
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M25PX32
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (Fast_Read), Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down (RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program (DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
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Instructions Table 5.
Instruction WREN WRDI RDID RDSR WRSR WRLR RDLR READ FAST_READ DOFR ROTP POTP PP DIFP SSE SE BE DP RDP
M25PX32 Instruction set
Description Write Enable Write Disable Read Identification 1001 1110 Read Status Register Write Status Register Write to Lock Register Read Lock Register Read Data Bytes Read Data Bytes at higher speed Dual Output Fast Read Read OTP (Read 64 bytes of OTP area) Program OTP (Program 64 bytes of OTP area) Page Program Dual Input Fast Program Subsector Erase Sector Erase Bulk Erase Deep Power-down Release from Deep Powerdown 0000 0101 0000 0001 1110 0101 1110 1000 0000 0011 0000 1011 0011 1011 0100 1011 0100 0010 0000 0010 1010 0010 0010 0000 1101 1000 1100 0111 1011 1001 1010 1011 9Eh 05h 01h E5h E8h 03h 0Bh 3Bh 4Bh 42h 02h A2h 20h D8h C7h B9h ABh 0 0 0 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 to 3 1 to 1 1 1 1 to 1 to 1 to 1 to 65 1 to 65 1 to 256 1 to 256 0 0 0 0 0 One-byte instruction Address Dummy code bytes bytes 0000 0110 0000 0100 1001 1111 06h 04h 9Fh 0 0 0 0 0 0 Data bytes 0 0 1 to 20
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M25PX32
Instructions
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 8. Write Enable (WREN) instruction sequence
S 0 C Instruction DQ0 High Impedance DQ1
AI13731
1
2
3
4
5
6
7
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Instructions
M25PX32
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write lo Lock Register (WRLR) instruction completion Page Program (PP) instruction completion Dual Input Fast Program (DIFP) instruction completion Program OTP (POTP) instruction completion Subsector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Write Disable (WRDI) instruction sequence
Figure 9.
S 0 C Instruction DQ0 High Impedance DQ1
AI13732
1
2
3
4
5
6
7
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M25PX32
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:

Manufacturer identification (one byte) Device identification (two bytes) A Unique ID code (UID) followed by 16 bytes of CFI data
The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (71h), and the memory capacity of the device in the second byte (16h). The UID is set to 10h and indicates that 16 bytes, related to the CFI content, are following. Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction should not be issued while the device is in Deep Power-down mode. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit Unique ID code followed by 16 bytes of CFI content will be shifted out on Serial Data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 6. Read Identification (RDID) data-out sequence
Device identification Manufacturer identification Memory type 20h 71h Memory capacity 16h 10h 16 bytes UID CFI content
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
S 0 C Instruction DQ0 Manufacturer Identification High Impedance DQ1 MSB 15 14 13 MSB 3 2 1 0 MSB
AI06809d
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification
UID + CFI Data
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Instructions
M25PX32
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 11. Table 7.
b7 SRWD 0 TB BP2 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Top/Bottom bit Block Protect bits Write Enable Latch bit Write In Progress bit
The status and control bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
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M25PX32
Instructions
6.4.4
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register (WRSR) instruction provided that the Write Enable (WREN) instruction has been issued. The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1, BP2) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array:

When TB is reset to `0' (default value), the area protected by the Block Protect bits starts from the top of the memory array (see Table 3: Protected area sizes) When TB is set to `1', the area protected by the Block Protect bits starts from the bottom of the memory array (see Table 3: Protected area sizes)
The TB bit cannot be written when the SRWD bit is set to `1' and the W pin is driven Low.
6.4.5
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (when the Status Register Write Disable (SRWD) bit is set to `1', and Write Protect (W/VPP) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence
S 0 C Instruction DQ0 Status Register Out High Impedance DQ1 7 MSB 6 5 4 3 2 1 0 7 MSB
AI13734
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
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Instructions
M25PX32
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data input (DQ0). The instruction sequence is shown in Figure 12. The Write Status Register (WRSR) instruction has no effect on b6, b1 and b0 of the Status Register. b6 is always read as `0'. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows the user to set and reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (HPM). The Write Status Register (WRSR) instruction is not executed once the hardware protected mode (HPM) is entered. Figure 12. Write Status Register (WRSR) instruction sequence
S 0 C Instruction Status Register In 7 High Impedance DQ1
AI13735
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
DQ0
6
5
4
3
2
1
0
MSB
30/63
M25PX32 Table 8.
W/VPP signal 1 0
Instructions Protection modes
SRWD bit 0 0 Software protected (SPM) Mode Write Protection of the Status Register Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Status Register is hardware write protected The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed Memory content Protected area(1) Unprotected area(1)
1
1
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
0
1
Hardware protected (HPM)
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 3
The protection features of the device are summarized in Table 8. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/VPP) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W/VPP) Low or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write Protect (W/VPP) High. If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
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Instructions
M25PX32
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
DQ0 High Impedance DQ1
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI13736
1. Address bits A23 to A22 are Don't care.
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M25PX32
Instructions
6.7
Read Data Bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at higher speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at higher speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at higher speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Read Data Bytes at higher speed (FAST_READ) instruction sequence and data-out sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31
DQ0 High Impedance DQ1
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte
DQ0
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI13737
DQ1
7 MSB
6
5
4
3
2
1. Address bits A23 to A22 are Don't care.
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Instructions
M25PX32
6.8
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed (FAST_READ) instruction. The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 15. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction. When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. Figure 15. Dual Output Fast Read instruction sequence
S Mode 3 C Mode 2 Instruction DQ0 24-bit address 23 22 21 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
DQ1
High Impedance
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte
DQ0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DATA OUT 1 DATA OUT 2 DQ1 7 MSB 5 3 1 7 MSB 5 3 1
DATA OUT 3 7 MSB 5 3 1
DATA OUT n 7 MSB 5 3 1 MSB
ai13574
1. A23 to A22 are Don't care.
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M25PX32
Instructions
6.9
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector. Each address bit is latched-in during the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output (DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 16. The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at any time during data output. Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Table 9.
Bit b7-b2 `1' b1 Sector Lock Down `0' `1' b0 Sector Write Lock `0' Write, Program and Erase operations in this sector are executed and will modify the sector contents.
Lock Register out(1)
Bit name Value Reserved The Write Lock and Lock Down bits cannot be changed. Once a `1' is written to the Lock Down bit it cannot be cleared to `0', except by a power-up. The Write Lock and Lock Down bits can be changed by writing new values to them. Write, Program and Erase operations in this sector will not be executed. The memory contents will not be changed. Function
1. Values of (b1, b0) after Power-up are defined in Section 7: Power-up and Power-down.
Figure 16. Read Lock Register (RDLR) instruction sequence and data-out sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
DQ0 High Impedance DQ1
23 22 21 MSB
3
2
1
0 Lock Register Out 7 6 5 4 3 2 1 0
MSB
AI13738
35/63
Instructions
M25PX32
6.10
Read OTP (ROTP)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 17. The address is automatically incremented to the next higher address after each byte of data is shifted out. There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read, since once the 65th byte has been read, the same (65th) byte keeps being read on the DQ1 pin. The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read OTP (ROTP) instruction issued while an Erase, Program or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress. Figure 17. Read OTP (ROTP) instruction and data-out sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31
DQ0 High Impedance DQ1
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte
DQ0
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT n 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI13573
DQ1
7 MSB
6
5
4
3
2
1. A23 to A7 are Don't care. 2. 1 n 65.
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M25PX32
Instructions
6.11
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Table 17: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed.
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Instructions Figure 18. Page Program (PP) instruction sequence
S 0 C Instruction 24-bit address Data byte 1 1 2 3 4 5 6 7 8 9 10
M25PX32
28 29 30 31 32 33 34 35 36 37 38 39
DQ0
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S
2072
2073
2074
2075
2076
2077
2
2078
1
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3
Data byte 256
DQ0
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
0
MSB
MSB
AI13739
1. Address bits A23 to A22 are Don't care.
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2079
M25PX32
Instructions
6.12
Dual Input Fast Program (DIFP)
The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Page Program (PP) instruction. The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 19. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see Table 17: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
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Instructions Figure 19. Dual Input Fast Program (DIFP) instruction sequence
M25PX32
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31
DQ0
23 22 21
3
2
1
0
DQ1
High Impedance
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C
DQ0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DATA IN 1 DQ1 7 5 3 1
DATA IN 2 7 MSB 5 3 1
DATA IN 3 7 5 3 1 7
DATA IN 4 5 3 1 7
DATA IN 5 5 3 1
DATA IN 256 7 MSB
AI14229
5
3
1
MSB
MSB
MSB
MSB
1. A23 to A22 are Don't care.
40/63
M25PX32
Instructions
6.13
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) bit. The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the instruction opcode, three address bytes and at least one data byte on Serial Data input (DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Program OTP instruction is not executed. There is no rollover mechanism with the Program OTP (POTP) instruction. This means that the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program, once all 65 bytes have been latched in, any following byte will be discarded. The instruction sequence is shown in Figure 20. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. To lock the OTP memory: Bit 0 of the OTP control byte, that is byte 64, (see Figure 21) is used to permanently lock the OTP memory array.

When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed. When bit 0 of byte 64 = `0', the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to `0', it can no longer be set to `1'. Therefore, as soon as bit 0 of byte 64 (control byte) is set to `0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in progress is rejected without having any effect on the cycle that is in progress.
41/63
Instructions Figure 20. Program OTP (POTP) instruction sequence
S 0 C Instruction 24-bit address Data byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
M25PX32
DQ0
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3 Data byte n
DQ0
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI13575
1. A23 to A7 are Don't care. 2. 1 n 65
Figure 21. How to permanently lock the 64 OTP bytes
64 data bytes OTP Control byte
Byte Byte Byte 0 1 2
Byte Byte 63 64
X
X
X
X
X
X
X
bit 0 When bit 0 = 0 the 64 OTP bytes become READ only
Bit 1 to bit 7 are NOT programmable
ai13587
42/63
M25PX32
Instructions
6.14
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed. Lock Register bits are volatile, and therefore do not require time to be written. When the Write to Lock Register (WRLR) instruction has been successfully executed, the Write Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value. Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 22. Write to Lock Register (WRLR) instruction sequence
S 0 C Instruction 24-Bit Address Lock Register In 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
DQ0
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
AI13740
Table 10.
Lock Register in(1)
Bit b7-b2 Value `0' Sector Lock Down bit value (refer to Table 9) Sector Write Lock bit value (refer to Table 9)
Sector
All sectors
b1 b0
1. Values of (b1, b0) after Power-up are defined in Section 7: Power-up and Power-down.
43/63
Instructions
M25PX32
6.15
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (DQ0). Any address inside the Subsector (see Table 4) is a valid address for the Subsector Erase (SSE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 23. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Subsector Erase (SSE) instruction issued to a sector that is hardware or software protected, is not executed. Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 23. Subsector Erase (SSE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
DQ0
23 22 MSB
2
1
0
AI13741
1. Address bits A23 to A22 are Don't care.
44/63
M25PX32
Instructions
6.16
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (DQ0). Any address inside the Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 24. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed. Figure 24. Sector Erase (SE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
DQ1
23 22 MSB
2
1
0
AI13742
1. Address bits A23 to A22 are Don't care.
45/63
Instructions
M25PX32
6.17
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 25. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 25. Bulk Erase (BE) instruction sequence
S 0 C Instruction DQ0 1 2 3 4 5 6 7
AI13743
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M25PX32
Instructions
6.18
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device is not in active use, as in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 16). To take the device out of Deep Power-down mode, the Release from Deep Power-down (RDP) instruction must be issued. No other instruction must be issued while the device is in Deep Power-down mode. The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 26. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 26. Deep Power-down (DP) instruction sequence
S 0 C Instruction DQ0 1 2 3 4 5 6 7 tDP
Standby mode
Deep Power-down mode
AI13744
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Instructions
M25PX32
6.19
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 27. The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the Standby mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 27. Release from Deep Power-down (RDP) instruction sequence
S 0 C Instruction DQ0 1 2 3 4 5 6 7 tRDP
High Impedance DQ1 Deep Power-down mode Standby mode
AI13745
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M25PX32
Power-up and Power-down
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down
A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR) and Write to Lock Register (WRLR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of:

tPUW after VCC has passed the VWI threshold tVSL after VCC has passed the VCC(min) level
These values are specified in Table 11. If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. After Power-up, the device is in the following state:

The device is in the Standby Power mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. The Write In Progress (WIP) bit is reset. The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0)
Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption may result.)
VPPH must be applied only when VCC is stable and in the VCCmin to VCCmax voltage range.
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Power-up and Power-down Figure 28. Power-up timing
VCC VCC(max) Program, Erase and Write commands are rejected by the device Chip Selection not allowed VCC(min) Reset state of the device VWI tPUW tVSL Read Access allowed
M25PX32
Device fully accessible
time
AI04009C
Table 11.
Symbol tVSL(1) tPUW(1) VWI(1)
Power-up timing and VWI threshold
Parameter VCC(min) to S low Time delay to write instruction Write Inhibit voltage Min. 30 1 1.5 10 2.5 Max. Unit s ms V
1. These parameters are characterized only.
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M25PX32
Initial delivery state
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device outside the ratings listed in Table 12: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 12.
Symbol TSTG TLEAD VIO VCC VPP VESD Storage temperature Lead temperature during soldering Input and output voltage (with respect to ground) Supply voltage Fast Program/Erase voltage Electrostatic discharge voltage (Human Body model)(2) -0.6 -0.6 -0.2 -2000
Absolute maximum ratings
Parameter Min. -65 Max. 150 see(1) VCC+0.6 4.0 10.0 2000 Unit C C V V V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 , R2 = 500 ).
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DC and AC parameters
M25PX32
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 13.
Symbol VCC VPPH TA TAVPP Supply voltage Supply voltage on VPP pin for Fast Bulk Erase mode Ambient operating temperature Ambient operating temperature for Fast Bulk Erase mode
Operating conditions
Parameter Min. 2.7 8.5 -40 15 25 Typ. Max. 3.6 9.5 85 35 Unit V V C C
Table 14.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input rise and fall times Input pulse voltages Input timing reference voltages Output timing reference voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max. Unit pF ns V V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 29. AC measurement I/O waveform
Input levels 0.8VCC Input and output timing reference levels 0.7VCC 0.5VCC 0.3VCC
AI07455
0.2VCC
Table 15.
Symbol CIN/OUT CIN
Capacitance(1)
Parameter Input/output capacitance (DQ0/DQ1) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V Min. Max. 8 6 Unit pF pF
1. Sampled only, not 100% tested, at TA=25 C and a frequency of 20 MHz.
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M25PX32 Table 16.
Symbol ILI ILO ICC1 ICC2
DC and AC parameters DC characteristics
Parameter Input leakage current Output leakage current Standby current Deep Power-down current S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9VCC at 75 MHz, DQ1 = open Operating current (READ) ICC3 Operating current (DOFR) Operating current (PP) ICC4 ICC5 ICC6 ICC7 ICCPP IPP VIL VIH VOL VOH Operating current (DIFP) Operating current (WRSR) Operating current (SE) Operating current (BE) Operating current for Fast Bulk Erase mode VPP operating current in Fast Bulk Erase mode Input low voltage Input high voltage Output low voltage Output high voltage IOL = 1.6 mA IOH = -100 A VCC-0.2 C = 0.1VCC / 0.9VCC at 33 MHz, DQ1 = open C = 0.1VCC / 0.9VCC at 75 MHz, DQ1 = open S = VCC S = VCC S = VCC S = VCC S = VCC S = VCC, VPP = VPPH S = VCC, VPP = VPPH - 0.5 0.7VCC 4 15 15 15 15 15 15 20 20 0.3VCC VCC+0.4 0.4 mA mA mA mA mA mA mA mA mA V V V V Test condition (in addition to those in Table 13) Min. Max. 2 2 50 10 12 Unit A A A A mA
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DC and AC parameters Table 17. AC characteristics(1)
Test conditions specified in Table 13 and Table 14 Symbol Alt. Parameter Clock frequency for the following instructions: DOFR, DIFP, FAST_READ, SSE, SE, BE, DP, WREN, WRDI, RDID, RDSR, WRSR, ROTP, PP, POTP, WRLR, RDLR, RDP Clock frequency for READ instructions tCLH Clock High time tCLL Clock Low time Clock rise time(5) (peak to peak) Clock fall time(5) (peak to peak) Min. Typ.(2)
M25PX32
Max.
Unit
fC
fC
D.C.
75
MHz
fR tCH(3) tCL(2) tCLCH(4) tCHCL
(4)
D.C. 6 6 0.1 0.1 5 5 2 5 5 5 100
33
MHz ns ns V/ns V/ns ns ns ns ns ns ns ns
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ
(4)
tCSS S active setup time (relative to C) S not active hold time (relative to C) tDSU Data In setup time tDH Data In hold time S active hold time (relative to C) S not active setup time (relative to C) tCSH S deselect time tDIS tV tHO Output Disable time Clock Low to Output valid under 30 pF
8 8 6 0 5 5 5 5 8 8 20 100 200 3 30
ns ns ns ns ns ns ns ns ns ns ns ns ns s s
tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(4) tHLQZ(4) tWHSL
(6)
Clock Low to Output valid under 10 pF Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C)
tLZ tHZ
HOLD to Output Low-Z HOLD to Output High-Z Write Protect setup time Write Protect hold time Enhanced Program supply voltage High (VPPH) to Chip Select Low S High to Deep Power-down mode S High to Standby mode
tSHWL(6) tVPPHSL(7) tDP(4) tRDP(4)
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M25PX32 Table 17. AC characteristics(1) (continued)
DC and AC parameters
Test conditions specified in Table 13 and Table 14 Symbol tW Alt. Parameter Write Status Register cycle time Page Program cycle time (256 bytes) tPP(8) Page Program cycle time (n bytes) Program OTP cycle time (64 bytes) tSSE tSE tBE
1. Preliminary data. 2. Typical values given for TA = 25 C. 3. tCH + tCL must be greater than or equal to 1/ fC 4. Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 7. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. 8. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) 9. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Min.
Typ.(2) 1.3 0.8 int(n/8) x 0.025(9) 0.2 70 1 34
Max. 15
Unit ms ms
5 ms 150 3 80 ms s s
Subsector Erase cycle time Sector Erase cycle time Bulk Erase cycle time Bulk Erase cycle time (VPP = VPPH)
17
Figure 30. Serial input timing
tSHSL S tCHSL C tDVCH tCHDX DQ0 MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
DQ1
High Impedance
AI13728
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DC and AC parameters
M25PX32
Figure 31. Write Protect Setup and Hold timing during WRSR when SRWD=1
W/VPP tWHSL
tSHWL
S
C
DQ0 High Impedance DQ1
AI07439c
Figure 32. Hold timing
S tHLCH tCHHL C tCHHH tHLQZ DQ1 tHHQX tHHCH
DQ0
HOLD
AI13746
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M25PX32 Figure 33. Output timing
S tCH C tCLQV tCLQX DQ1 tQLQH tQHQL ADDR. DQ0 LSB IN tCLQX tCLQV tCL
DC and AC parameters
tSHQZ
LSB OUT
AI13729
Figure 34. VPPH timing
End of BE (identified by WIP polling)
S
C
DQ0
BE
VPPH VPP
tVPPHSL ai13726
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Package mechanical
M25PX32
11
Package mechanical
Figure 35. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 x 5 mm, package outline
A R1 D1 B
MCAB bbb
D
aaa C A
E
E1
E2
e
2x
0.10 C B
aaa C B
b
0.10 C A
A2
D2 L
ddd
A
A1 A3
C
70-ME
1. Drawing is not to scale.
Table 18.
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 x 5 mm, package mechanical data
millimeters inches Max 1.00 0.05 0.0256 0.0079 0.35 0.48 0.0157 0.2362 0.2264 3.20 3.60 0.1339 0.1969 0.1870 3.80 - 0.00 0.50 0.75 12 0.15 0.10 0.05 4.30 - 0.1575 0.0500 0.0039 0.0236 0.1496 - 0.0000 0.0197 0.0295 12 0.0059 0.0039 0.0020 0.1693 - 0.1260 0.1417 0.0138 0.0189 Typ 0.0335 Min 0.0315 0.0000 Max 0.0394 0.0020
Symbol Typ A A1 A2 A3 b D D1 D2 E E1 E2 e R1 L aaa bbb ddd 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.10 0.60 0.85 Min 0.80 0.00
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M25PX32
Package mechanical Figure 36. SO8W 8 lead plastic small outline, 208 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 19.
SO8W 8 lead plastic small outline, 208 mils body width, package mechanical data
millimeters inches Max 2.50 0.00 1.51 0.40 0.20 0.35 0.10 0.25 2.00 0.51 0.35 0.10 6.05 5.02 7.62 1.27 - 0 0.50 8 6.22 8.89 - 10 0.80 0.050 0.198 0.300 - 0 0.020 8 0.016 0.008 0.000 0.059 0.014 0.004 Typ Min Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 - 10 0.031
Symbol Typ A A1 A2 b c CP D E E1 e k L N Min
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Package mechanical
M25PX32
Figure 37. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline
D
16 9
h x 45
C E H
1
8
A2 A ddd A1 L
B SO-H
e
1. Drawing is not to scale.
Table 20.
SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data
millimeters inches Max 2.65 0.30 0.51 0.32 10.50 7.60 - 10.65 0.75 1.27 8 0.10 0.050 Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 - 0.394 0.010 0.016 0 Max 0.104 0.012 0.020 0.013 0.413 0.299 - 0.419 0.030 0.050 8 0.004
Symbol Typ A A1 B C D E e H h L ddd 1.27 Min 2.35 0.10 0.33 0.23 10.10 7.40 - 10.00 0.25 0.40 0
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M25PX32
Part numbering
12
Part numbering
Table 21.
Example:
Ordering information scheme
M25PX32 - V MW 6 E
Device type M25PX = serial Flash memory, 4-Kbyte and 64-Kbyte erasable sectors, dual input/output
Device function 32 = 32 Mbit (4 Mb x 8)
Operating voltage V = VCC = 2.7 V to 3.6 V
Package MW = SO8W (208 mils width) MF = SO16 (300 mils width) MP = VFQFPN 6 x 5 mm (MLP8)
Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow
Option E = Standard Packing ECOPACK(R) (RoHS compliant) F = Tape & Reel Packing ECOPACK(R) (RoHS compliant)
Note: Note: 1
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. Secure options are available on customer requests. For example, main sectors can be configured as OTP protected areas and the memory can be protected during power-up. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Revision history
M25PX32
13
Revision history
Table 22.
Date 19-Dec-2006
Document revision history
Revision 0.1 Initial release. Document status promoted from Target Specification to Preliminary Data. Added the SO16 (MF) package. Added specific hardware protection (see Section 4.8.2: Specific hardware and software protection). Modified the RDID instruction (see Section 6.3: Read Identification (RDID)). Updated the typical value for the Deep Power-down current (ICC2). Modified Lock Registers' configuration in Section 7: Power-up and Powerdown. Changes
31-Jul-2007
1
20-Aug-2007
2
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M25PX32
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